A NAND flash is a semiconductor storage device for storing data without being supplied with power. Thus, the NAND flash is used for backing up data in a cache memory in the storage device during blackout, for example.
When data is backed up in the storage device, parity data is added to the backed-up data to enable the data to be recovered when an error occurs in the data. Data backup into the NAND flash will be described with reference to FIG. 8.
FIG. 8 is a diagram illustrating an exemplary NAND flash control device according to a related technique. As illustrated in FIG. 8, a NAND flash control device 800 is connected to NAND flashes 910 to 940 configuring RAID (Redundant Arrays of Inexpensive Disks), respectively. Each of the NAND flashes 910 to 940 has a buffer and an array. The NAND flashes 910 to 930 store user data therein. The NAND flash 940 stores parity data therein.
In the example illustrated in FIG. 8, only a write DMA (Direct Memory Access) 810 among the DMAs provided in the NAND flash control device 800 is illustrated. The write DMA 810 includes a write unit 811, a parity generation unit 812, and a parity calculation RAM (Random Access Memory) 813.
There will be described below with reference to FIG. 9 a case in which in the NAND flash control device 800, user data is divided into three stripes to be written into the NAND flashes 910 to 930 and parity data is written into the NAND flash 940 by way of example. FIG. 9 is a sequence diagram illustrating data write operations by the NAND flash control device.
In the NAND flash control device 800, the first stripe is input into the write unit 811 and the parity generation unit 812. The write unit 811 writes the first stripe into a buffer 911 in the NAND flash 910 (step S901), and at the same time, the parity generation unit 812 writes the first stripe into the parity calculation RAM 813. Subsequently, in the NAND flash 910, the stripe written into the buffer 911 is written into an array 912 (step S902).
In the NAND flash control device 800, the second stripe is input into the write unit 811 and the parity generation unit 812. The write unit 811 writes the second stripe into a buffer 921 in the NAND flash 920 (step S903), and at the same time, the parity generation unit 812 performs the following processings. That is, the parity generation unit 812 reads the first stripe from the parity calculation RAM 813, and calculates parity data based on XOR with the second stripe and writes it into the parity calculation RAM 813. Subsequently, in the NAND flash 920, the stripe written into the buffer 921 is written into an array 922 (step S904).
Subsequently, in the NAND flash control device 800, the third stripe is input into the write unit 811 and the parity generation unit 812. The write unit 811 writes the third stripe into a buffer 931 in the NAND flash 930 (step S905), and at the same time, the parity generation unit 812 performs the following processings. That is, the parity generation unit 812 reads the parity data from the parity calculation RAM 813, and calculates parity data based on XOR with the third stripe and writes it into the parity calculation RAM 813. Subsequently, in the NAND flash 930, the stripe written into the buffer 931 is written into an array 932 (step S906).
After finishing writing the three stripes into the arrays in the NAND flashes, respectively, the write unit 811 reads the parity data from the parity calculation RAM 813 and writes the parity data into a buffer 941 in the NAND flash 940 (step S907). Then, in the NAND flash 940, the parity data written into the buffer 941 is written into an array 942 (step S908).
In this way, in the storage device, the data in the cache memory is saved into the NAND flashes to be backed up during blackout. There is known a technique in which when power is resumed while the blackout processing is being performed, unnecessary blackout processings or power resumption processings may be omitted.
Patent Literature 1: International Publication Pamphlet No. WO 2009/098776    Patent Literature 2: Japanese Laid-open Patent Publication No. 2005-182983
However, the related technique has a problem that a write capability is lowered by writing parity data.
In the example illustrated in FIG. 9, in the NAND flash control device 800, the third stripe is written into the array 932 in the NAND flash 930 and then parity data is written into the NAND flash 940. Thus, a user data writing end time delays by a time for writing the parity data.